DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 210

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 6.25 shows the timing for transition to the bus-released state.
6.9.1
When MSTPCR is set to H'FFFFFF and transmitted to sleep mode, the external bus release does
not function. To activate the external bus release in sleep mode, do not set MSTPCR to H'FFFFFF.
Rev.7.00 Dec. 24, 2008 Page 154 of 698
REJ09B0074-0700
Address bus
HWR, LWR
Data bus
Bus Release Usage Note
Note : n = 0 to 5
[1]
[2]
[3]
[4]
[5]
BREQ
BACK
CSn
RD
AS
φ
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external bus
master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
Figure 6.25 Bus-Released State Transition Timing
T
0
CPU cycle
T
Address
1
[1]
Minimum
1 state
T
2
[2]
2
[3]
state.
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
CPU
cycle
[5]