DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 552

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Notes: 1. EP0 interrupts must be assigned to the same interrupt request signal.
• EXIRQ0 signal
• EXIRQ1 signal
• IRQ6 signal
Rev.7.00 Dec. 24, 2008 Page 496 of 698
REJ09B0074-0700
Register
UIFR3
The EXIRQ0 signal requests interrupt sources for which the corresponding bits in interrupt
select registers 0 to 3 (UISR0 to UISR3) are cleared to 0. The EXIRQ0 is driven low if a
corresponding bit in the interrupt flag register is set to 1.
The EXIRQ1 signal requests interrupt sources for which the corresponding bits in interrupt
select registers 0 to 3 (UISR0 to UISR3) are cleared to 0. The EXIRQ1 is driven low if a
corresponding bit in the interrupt flag register is set to 1.
The IRQ6 signal is specific to the suspend/resume interrupt request. The falling edge of the
IRQ6 signal is output at the transition from the suspend state or from the resume state.
2. An EP1 DMA transfer by a USB request is specified by the EP1T1 and EP1T0 bits in
3. An EP2 DMA transfer by a USB request is specified by the EP2T1 and EP2T0 bits in
4. The suspend/resume interrupt request IRQ6 must be specified to be detected at the
5. The DREQ signal is not used for auto-request. The CPU can activate the DMAC using
UDMAR.
UDMAR.
falling edge (IRQ6SCB and IRQ6SCA in ISCRH = 01) by the interrupt controller register.
any flags and interrupts.
Bit
0
1
2
3
4
5
6
7
Transfer
Mode
(Status)
Interrupt
Source
VBUSi
(VBUSs)
SPRSi
(SPRSs)
Reserved
SETC
SOF
CK48READY
Description
VBUS interrupt
VBUS status
Suspend/resume
interrupt
Suspend/resume
status
Set_Configuration
detection
Start of Frame packet
detection
USB operating clock
stabilization detection
Interrupt
Request
Signal
EXIRQ0 or
EXIRQ1
×
IRQ6 *
×
EXIRQ0 or
EXIRQ1
EXIRQ0 or
EXIRQ1
EXIRQ0 or
EXIRQ1
4
DMAC
Activation by
USB
Request*
×
×
×
×
×
×
×
5

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