DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 584

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.8.4
The following must be noted for the EP0s FIFO used to receive 8-byte setup data. The USB is
designed to always receive setup commands. Accordingly, write from the UDC has higher priority
than read from the LSI. If the reception of the next setup command starts while the LSI is reading
data after completing reception, this data read from the LSI is forcibly cancelled and the next setup
command write starts. After the next setup command write, data read from the LSI is thus
undefined. Read operation is forcibly disabled because data cannot be guaranteed if DP-RAM used
as FIFO accesses the same address for write and read.
14.8.5
If the USB cable is disconnected during communication, old data may be contained in the FIFO.
Accordingly, FIFOs must be cleared immediately after USB cable connection. In addition, after
bus reset, all FIFOs must also be cleared. Note, however, that FIFOs that are currently used for
data transfer to or from the host must not be cleared.
14.8.6
A suspend/resume interrupt requested by IRQ6 must be specified as falling-edge sensitive.
14.8.7
When the CPU reads or writes to data registers, the following must be noted:
• Transmit data registers (UEDR0i, UEDR3, UEDR1)
• Receive data registers (UEDR0o, UEDR2)
Rev.7.00 Dec. 24, 2008 Page 528 of 698
REJ09B0074-0700
Data to be written to the transmit data registers must be within the maximum packet size. For
the transmit data register of EP1 having a dual-FIFO configuration, data to be written at any
time must be within the maximum packet size. In this case, after a data write, the FIFO is
switched to the other FIFO, enabling an further data write, when the PKTE bit in UTRG0 is set
to 1. Accordingly, data of size corresponding to two FIFOs must not be written to the transmit
data registers at a time.
Receive data registers must not read a data size that is greater than the effective size of the read
data item. In other words, receive data registers must not read data with data size larger than
that specified by the receive data size register. For the receive data register of EP2 having a
dual-FIFO configuration, data to be read at any time must be within the maximum packet size.
In this case, after reading the currently selected FIFO, set the RDFN bit in UTRG to 1. This
switches the FIFO to the other FIFO and updates the receive data size, enabling the next data
read. In addition, if there is no receive data in a FIFO, data must not be read. Otherwise, the
Setup Data Reception
FIFO Clear
IRQ6 Interrupt
Data Register Overread or Overwrite