DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 594

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.3.1
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are
shown in table 15.2.
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading the ADDR, read the upper byte before the lower byte, or read in word unit. The
initial value of the ADDR is H'0000.
Table 15.2 Analog Input Channels and Corresponding ADDR Registers
15.3.2
ADCSR controls A/D conversion operations.
Rev.7.00 Dec. 24, 2008 Page 538 of 698
REJ09B0074-0700
Analog Input Channel
AN0
AN1
AN2, AN14
AN3, AN15
Bit
7
Bit Name Initial Value
ADF
A/D Data Registers A to D (ADDRA to ADDRD)
A/D Control/Status Register (ADCSR)
0
A/D Data Register to Be Stored the Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD
R/W
R/(W)* A/D End Flag
Description
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
When 0 is written after reading ADF = 1
When DMAC is activated by an ADI interrupt and
ADDR is read
specified in scan mode
When A/D conversion ends in single mode
When A/D conversion ends on all channels