DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 397

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note: * The write value should always be 0 to clear this flag.
Bit
7
6
5
4, 3
2
1
0
Bit Name
OVF
WT/IT
TME
—
CKS2
CKS1
CKS0
Initial Value
0
0
0
All 1
0
0
0
R/W
R/(W)*
R/W
R/W
—
R/W
R/W
R/W
Description
Overflow Flag
Indicates that TCNT has overflowed. Only a write of
0 is permitted, to clear the flag.
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
When polling CVF when the interval timer interrupt
has been prohibited, OVF = 1 status should be read
two or more times.
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: Interval timer mode
1: Watchdog timer mode
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and
is initialized to H'00.
Reserved
These bits are always read as 1 and cannot be
modified.
Clock Select 0 to 2
Selects the clock source to be input to TCNT. The
overflow frequency for φ = 16 MHz is enclosed in
parentheses. The overflow period is the time from
when TCNT starts counting up from H'00 until
overflow occurs.
000: Clock φ/2 (frequency: 32.0 μs)
001: Clock φ/64 (frequency: 1.0 ms)
010: Clock φ/128 (frequency: 2.0 ms)
011: Clock φ/512 (frequency: 8.2 ms)
100: Clock φ/2048 (frequency: 32.8 ms)
101: Clock φ/8192 (frequency: 131.1 ms)
110: Clock φ/32768 (frequency: 524.3 ms)
111: Clock φ/131072 (frequency: 2.1 s)
Rev.7.00 Dec. 24, 2008 Page 341 of 698
REJ09B0074-0700