DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 251

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
Activation by USB Request: The USB request (DREQ signal) is specified as a DMAC activation
source. The USB request is generated by the level sense. In full-address normal mode, the USB
request is carried out as follows.
While the DREQ signal is kept high, the DMAC waits for the transfer request. While the DREQ
signal is kept low, the DMAC releases the bus each time a byte is transferred and the transfer is
performed continuously. When the DREQ signal is driven high during the transfer, the transfer is
halted and the DMAC waits for the transfer request.
Activation by Auto-Request: Auto-request activation is performed by register setting only, and
transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be
selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession
of the bus until the end of the transfer, and transfer is performed continuously.
Rev.7.00 Dec. 24, 2008 Page 195 of 698
REJ09B0074-0700