DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 258

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4.10
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.9
summarizes the priority order for DMAC channels.
Table 7.9
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the highest-
priority channel from among those issuing a request according to the priority order shown in table
7.9. During burst transfer, or when one block is being transferred in block transfer, the channel will
not be changed until the end of the transfer. Figure 7.20 shows a transfer example in which transfer
requests are issued simultaneously for channels 0A, 0B, and 1.
Rev.7.00 Dec. 24, 2008 Page 202 of 698
REJ09B0074-0700
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
Address bus
DMA control
Channel 0A
Channel 0B
Channel 1
HWR
LWR
DMAC Multi-Channel Operation
RD
φ
release
DMAC Channel Priority Order
Idle
Bus
Request clear
Read
DMA read
Request
hold
Request
hold
Figure 7.20 Example of Multi-Channel Transfer
Write
Channel 0A
transfer
Selection
DMA write
selection
Non-
Idle
Full Address Mode
Channel 0
Channel 1
release
Request clear
Bus
Read
DMA read
Request
hold
Write
Channel 0B
transfer
Selection
DMA write
Idle
release
Request clear
Bus
Read
DMA read
Channel 1 transfer
Write
High
Low
Priority
DMA write
Read
DMA
read