DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 635

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.8
A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: program mode, erase mode, program-verify mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 17.8.1, Program/Program-Verify and section 17.8.2,
Erase/Erase-Verify, respectively.
17.8.1
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in Figure 17.13 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be written to the flash memory without subjecting the
chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128-
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
5. The time during which the P1 bit is set to 1 is the programming time. Figure 17.13 shows the
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
8. The maximum number of repetitions of the program/program-verify sequence to the same bit is
programming has already been performed.
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
Figure 17.13.
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
allowable programming times.
An overflow cycle of approximately (y + z1 + α + β) μs is allowed.
is B'0. Verify data can be read in words from the address to which a dummy write was
performed.
(N1 + N2).
Flash Memory Programming/Erasing
Program/Program-Verify
Rev.7.00 Dec. 24, 2008 Page 579 of 698
REJ09B0074-0700