DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 684
DF2218BR24V
Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of DF2218BR24V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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20.12
20.12.1 I/O Port Status
In software standby mode or watch mode, I/O port states are retained. In addition, if the OPE bit is
set to 1, the address bus and bus control signal output are retained. Therefore, there is no reduction
in current dissipation for the output current when a high-level signal is output.
20.12.2 Current Dissipation during Oscillation Stabilization Wait Period
Current dissipation increases during the oscillation stabilization wait period.
20.12.3 Flash Memory Module Stop
Setting of the flash memory module stop mode should be carried out while the programs in the on-
chip RAM and external memory are executed. For details, see section 20.1.3, Module Stop Control
Registers A to C (MSTPCRA to MSTPCRC).
20.12.4 DMAC Module Stop
Depending on the operating status of the DMAC, the MSTPA7 bit may not be set to 1. Setting of
the DMAC module stop mode should be carried out only when the DMAC is not activated.
For details, section 7, DMA Controller (DMAC).
20.12.5 On-Chip Peripheral Module Interrupt
• Module stop mode
• Subactive Mode/Watch Mode
Rev.7.00 Dec. 24, 2008 Page 628 of 698
REJ09B0074-0700
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if
module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or DMAC activation source. Interrupts should therefore be
disabled before setting module stop mode.
On-chip peripheral modules (DMAC and TPU) that stop operation in subactive mode cannot
clear interrupts in subactive mode. Therefore, if subactive mode is entered when an interrupt is
requested, CPU interrupt factors cannot be cleared.
Interrupts should therefore before executing the SLEEP instruction and entering subactive or
watch mode.
Usage Notes
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