DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 599

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.5.2
In scan mode, A/D conversion is to be performed sequentially on the specified channels (four
channels maximum). The operations are as follows.
1. When the ADST bit is set to 1 by software, TPU or external trigger input, A/D conversion
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF flag is set to 1. If the
4. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
channel 2 (AN2)
channel 3 (AN3)
channel 0 (AN0)
channel 1 (AN1)
starts on the first channel in the group (AN0 when CH3 and CH2 = 00, AN4 when CH3 and
CH2 = 01, or AN8 when CH3 and CH2 = 10).
the A/D data register corresponding to each channel.
ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
Conversion of the first channel in the group starts again.
cleared to 0, A/D conversion stops.
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
State of
State of
State of
State of
Figure 15.4 A/D Conversion Timing (Scan Mode, Channels AN0 to AN2 Selected)
ADDRA
ADDRB
ADDRC
ADDRD
ADST
ADF
Scan Mode
2. Data currently being converted is ignored.
Idle
Idle
A/D conversion 1
Set*
Idle
1
A/D conversion 2
Transfer
Continuous A/D conversion execution
A/D conversion result 1
Idle
A/D conversion 3
Idle
Rev.7.00 Dec. 24, 2008 Page 543 of 698
Idle
A/D conversion 4
A/D conversion time
A/D conversion result 2
A/D conversion result 3
A/D conversion 5
A/D conversion result 4
REJ09B0074-0700
*
2
Clear*
Idle
Idle
Idle
1
Clear*
1

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