DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 577

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Accordingly, this processing is automatically performed only when 64-byte data is sent. This
processing is not performed automatically when data less than 64 bytes is sent.
(b) EP1 DMA transfer procedure
1. Set the bits EP1T1 and EP1T0 in UDMAR.
2. Set DMAC (specifies the number of transfers in DMAC to transmit 150 bytes of data).
3. Activate DMAC.
4. Perform DMA transfer.
5. Write 1 to the EP1PKTE bit in UTRG0 by a DMA transfer end interrupt.
(4) EP2 DMA Transfer
The EP2T1 bit in UDMAR enables the DMA transfer. The EP2T0 bit in the UDMAR specifies the
DREQ signal to be used by the DMA transfer. When 1 is written to the EP2T1 bit, the DREQ
signal is driven low if at least one of EP2 data FIFOs is full (ready state); the DREQ signal is
driven high if both EP2 data FIFOs are empty when all receive data items are read.
(a) EP2RDFN in UTRG0
When DMA transfer is performed on EP2 receive data, do not write 1 to EP2RDFN after one data
FIFO (64 bytes) has been read. In data transfer other than DMA transfer, the next data cannot be
read after one data FIFO (64 bytes) has been read unless 1 is written to EP2RDFN. While in DMA
transfer, the USB module automatically performs the same processing as writing 1 to EP2RDFN if
the currently selected data FIFO becomes empty. Accordingly, in DMA transfer, the user needs
not to write 1 to EP2RDFN. If the user writes 1 to EP2RDFN in DMA transfer, excess transfer
occurs and correct operation cannot be guaranteed.
Figure 14.23 shows an example of EP2 receiving 150 bytes of data from the host. In this case,
internal processing as the same as writing 1 to EP2RDFN is automatically performed three times.
This kind of internal processing is performed when the currently selected data FIFO becomes
empty. Accordingly, this processing is automatically performed both when 64-byte data is sent and
when data less than 64 bytes is sent.
64 bytes
Figure 14.22 EP1PKTE Operation in UTRG0
EP1PKTE
(Automatically
performed)
64 bytes
EP1PKTE
(Automatically
performed)
Rev.7.00 Dec. 24, 2008 Page 521 of 698
22 bytes
Executed by DMA transfer
end interrupt (user)
EP1PKTE is
not performed
REJ09B0074-0700