DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 563

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Setup Stage
Notes: 1. In the setup stage, the firmware first analyzes the command data that is sent from the host and
Receive 8-byte command
(SetupTS in UIFR0 = 1)
Receive SETUP token
2. When the transfer direction is control-out, the EP0i transfer request interrupt that is required in the
Set setup command
recive complete flag
to be processed by
data in UEDR0s
required to be processed by the firmware, and determines subsequent processing.
(For example, the data stage direction.)
status stage should be enabled. When the transfer direction is control-in, this interrupt is not
required and must be disabled.
To data stage
USB function
Command
firmware?
Yes
Figure 14.12 Setup Stage Operation
No
processing by
EXIRQx
this module
Automatic
Clear EP0o FIFO (EP0oCLR in UFCLR = 1)
Rev.7.00 Dec. 24, 2008 Page 507 of 698
Clear EP0i FIFO (EP0iCLR in UFCLR = 1)
To control-in
data stage
Write 1 to EP0s read complete bit
Determine data stage direction*
Read 8-byte data from UEDR0s
(EP0sRDFN in UTRG0 = 1)
(SetupTS in UIFR0 = 0)
Decode command data
Clear SetupTS flag
Firmware
*
2
To control-out
data stage
REJ09B0074-0700
1