DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 597

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.4
ADDRA to ADDRD are 16-bit registers. As the data bus to the bus master is 8 bits wide, the bus
master accesses to the upper byte of the registers directly while to the lower byte of the registers
via the temporary register (TEMP).
Data in ADDR is read in the following way: When the upper-byte data is read, the upper-byte data
will be transferred to the CPU and the lower-byte data will be transferred to TEMP. Then, when
the lower-byte data is read, the lower-byte data will be transferred to the CPU.
When data in ADDR is read, the data should be read from the upper byte and lower byte in the
order. When only the upper-byte data is read, the data is guaranteed. However, when only the
lower-byte data is read, the data is not guaranteed.
Figure 15.2 shows data flow when accessing to ADDR.
Interface to Bus Master
Bus master
Bus master
(H'AA)
(H'40)
Read the upper byte
Read the lower byte
Figure 15.2 Access to ADDR (When Reading H'AA40)
Bus interface
Bus interface
ADDRnH
ADDRnH
(H'AA)
(H'AA)
Rev.7.00 Dec. 24, 2008 Page 541 of 698
Module data bus
ADDRnL
Module data bus
ADDRnL
TEMP
(H'40)
(H'40)
TEMP
(H'40)
(H'40)
(n = A to D)
(n = A to D)
REJ09B0074-0700

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