DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 430

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Legend:
×: Don’t care
Rev.7.00 Dec. 24, 2008 Page 374 of 698
REJ09B0074-0700
Bit
3
2
1
0
Bit Name Initial Value
MPIE
TEIE
CKE1
CKE0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
0×: Internal clock (SCK pin functions as clock output)
1×: External clock (SCK pin functions as clock input)
Description
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the multiprocessor
bit is 1, this bit is automatically cleared and normal
reception is resumed. For details, refer to section 12.5,
Multiprocessor Communication Function.
When receive data including MPB = 0 is received,
receive data transfer from RSR to RDR, receive error
detection, and setting of the RDRF, FER, and ORER
flags in SSR, is not performed. When receive data
including MPB = 1 is received, the MPB bit in SSR is set
to 1, the MPIE bit is cleared to 0 automatically, and
generation of RXI and ERI interrupts (when the TIE and
RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
Transmit End Interrupt Enable
This bit is set to 1, TEI interrupt request is enabled. TEI
cancellation can be performed by reading 1 from the
TDRE flag in SSR, then clearing it to 0 and clearing the
TEND flag to 0, or clearing the TEIE bit to 0.
Clock Enable 0 and 1
Selects the clock source and SCK pin function.
Asynchronous mode
00: Internal baud rate generator
01: Internal baud rate generator
1×: External clock
Clocked synchronous mode
SCK pin functions as I/O port
Outputs a clock of the same frequency as the bit
rate from the SCK pin.
Inputs a clock with a frequency 16 times the bit rate
from the SCK pin.