DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 543

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3.24 USB Interrupt Select Register 3 (UISR3)
UISR3 sets EXIRQ to output interrupt request indicated in the interrupt flag register 3 (UIFR3).
When a bit in UIER3 corresponding to the UISR3 bit is cleared to 0, an interrupt request is output
from EXIRQ0. When a bit in UIER3 corresponding to the UISR3 bit is set to 1, an interrupt
request is output from EXIRQ1.
14.3.25 USB Data Status Register (UDSR)
UDSR indicates whether the IN FIFO data registers (EP1, and EP3) contain valid data or not. A bit
in USDR is set when data written to the corresponding IN FIFO becomes valid after the
corresponding PKTE bit in UTRG is set to 1. A bit in USDR is cleared when all valid data is sent
to the host. For EP1, having a dual-FIFO configuration, the corresponding bit in USDR is cleared
to 0 and FIFO becomes empty.
Bit
7
6
5
4 to 1 —
0
Bit Name
CK48READYS 0
SOFS
SETCS
VBUSiS
Initial Value R/W
0
0
All 0
0
R/W
R/W
R/W
R
R/W
Description
Selects the CK48READY interrupt.
Selects the SOF interrupt.
Selects the SETC interrupt.
Reserved
These bits are always read as 0.
Selects the VBUSi interrupt.
Rev.7.00 Dec. 24, 2008 Page 487 of 698
REJ09B0074-0700