DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 518

IC H8S/2218 MCU FLASH 112-LFBGA

DF2218BR24V

Manufacturer Part Number
DF2218BR24V
Description
IC H8S/2218 MCU FLASH 112-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2218BR24V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
112-LFBGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2218BR24V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
13.4
13.4.1
Figure 13.3 shows the TAP controller status transition diagram, based on the JTAG standard.
Note: The transition condition is the TMS value at the rising edge of TCK. The TDI value is
Rev.7.00 Dec. 24, 2008 Page 462 of 698
REJ09B0074-0700
TFP-100G
TFP-100GV
Pin No.
80
81
sampled at the rising edge of the TCK and shifted at the falling edge of the TCK. The
TDO value changes at the falling edge of the TCK. In addition, TDO is high-impedance
state in a state other than Shift-DR or Shift-IR state. If TRST is 0, Test-Logic-Reset state
is entered asynchronously with the TCK.
TAP Controller
Boundary Scan Function Operation
BP-112
BP-112V
Pin No.
A9
C8
1
1
0
Test-Logic-Reset
Run-Test/Idle
Select-DR
Capture-DR
Update-DR
1
Exit1-DR
Shift-DR
Figure 13.3 TAP Controller Status Transition
1
1
1
0
0
0
0
Pin Name
FWE
NMI
0
0
1
Pause-DR
Exit2-DR
1
to TDO
0
0
1
0
1
Capture-IR
Update-IR
Select-IR
Exit1-IR
Shift-IR
1
1
0
0
0
1
IN
IN
I/O
0
1
Pause-IR
Exit2-IR
1
Bit Name
1
0
0
0

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