DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 237

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4.3
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The
transfer direction can be specified by the DTDIR bit in DMACR. Table 7.4 summarizes register
functions in idle mode.
Table 7.4
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.4
illustrates operation in idle mode.
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If
the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU. The maximum number
of transfers, when H'0000 is set in ETCR, is 65,536.
Register
23
23
H'FF
15
15
Idle Mode
ETCR
MAR
MAR
Register Functions in Idle Mode
IOAR
0
0
0
DTDIR = 0
Source
address
register
Destination
address
register
Transfer counter
Figure 7.4 Operation in Idle Mode
Function
DTDIR = 1
Destination
address
register
Source
address
register
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Initial Setting
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Rev.7.00 Dec. 24, 2008 Page 181 of 698
Operation
Fixed
Fixed
transfer, transfer
ends when count
reaches H'0000
REJ09B0074-0700
IOAR