DF2218BR24V Renesas Electronics America, DF2218BR24V Datasheet - Page 289

• Manufacturer Part Number: DF2218BR24V
• Description: IC H8S/2218 MCU FLASH 112-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2218BR24V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-LFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.6
In the H8S/2218 Group, the port A is a 4-bit I/O port also functioning as address bus (A19 to A16)
output pins and SCI I/O pins. In the H8S/2212 Group, the port A is a 3-bit I/O port also
functioning as SCI I/O pins. The port A has the following registers.
• Port A data direction register (PADDR)
• Port A data register (PADR)
• Port A register (PORTA)
• Port A pull-up MOS control register (PAPCR)
• Port A open-drain control register (PAODR)
8.6.1
PADDR specifies input or output for the pins of the port A.
Since PADDR is a write-only register, the bit manipulation instructions must not be used to write
PADDR. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
Note: * Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read. This bit
Bit
7 to
4
3
2
1
0
Bit Name Initial Value
⎯
PA3DDR
PA2DDR
PA1DDR
PA0DDR*
cannot be modified.
Port A
Port A Data Direction Register (PADDR)
Undefined
0
0
0
0
R/W
⎯
W
W
W
W
Reserved
These bits are undefined and cannot be modified.
(H8S/2218 Group)
Modes 4 to 6:
If address output is enabled by the setting of bits AE3 to
AE0 in PFCR, the corresponding port A pins are address
outputs. When address output is disabled, setting a
PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an
input port.
Mode 7:
Setting a PADDR bit to 1 makes the corresponding port A
pin an output port, while clearing the bit to 0 makes the
pin an input port.
(H8S/2212 Group)
Setting a PADDR bit to 1 makes the corresponding port A
pin an output port, while clearing the bit to 0 makes the
pin an input port.
Description
Rev.7.00 Dec. 24, 2008 Page 233 of 698
REJ09B0074-0700