UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 169

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UPD70F3201YGC-YEU-A

Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet

Specifications of UPD70F3201YGC-YEU-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2) Registers
Note When reading or writing bits 8 to 15 of the PDL register in 8-bit or 1-bit units, specify these bits as bits 0
Remarks 1. In input mode: When port DL (PDL) is read, the pin level at that time is read. When written, the
(a) Port register DL (PDL)
to 7 of the PDLH register.
Port register DL (PDL) is a 16-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
If the higher 8 bits of the PDL register are used as PDLH, and the lower 8 bits as PDLL, however, PDLH
and PDLL can be used as an 8-bit I/O port whose input or output can be manipulated in 8-bit or 1-bit units.
PDL (PDLH
2. After reset, an undefined value (pin input level) is read from PDL in the input mode. When PDL is
In output mode: When port DL (PDL) is read, the value of PDL is read. When a value is written to
read in the output mode, 0000H (value of the output latch) is read.
(PDLL)
After reset: Undefined
Note
)
PDL15
PDLn
PDL7
15
0
1
data written to PDL is written. The input pin is not affected.
PDL, it is immediately output.
Outputs 0.
Outputs 1.
PDL14
PDL6
14
CHAPTER 4 PORT FUNCTIONS
R/W
User’s Manual U15905EJ2V1UD
Controls output data (in output mode) (n = 0 to 15)
PDL13
PDL5
13
Address: PDL
PDL12
PDL4
12
PDLL FFFFF004H, PDLH FFFFF005H
FFFFF004H,
PDL11
PDL3
11
PDL10
PDL2
10
PDL9
PDL1
9
PDL8
PDL0
8
167

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