UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 190

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UPD70F3201YGC-YEU-A

Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet

Specifications of UPD70F3201YGC-YEU-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5.6
5.6.1
188
(1) Data wait control register 0 (DWC0)
Caution Be sure to clear bits 15, 11, 7, and 3 to 0.
Wait Function
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus
cycle that is executed for each CS space.
The number of wait states can be programmed by using data wait control register 0 (DWC0). Immediately after
system reset, 7 data wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
Programmable wait function
DWC0
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do
After reset:
CSn signal
CSn signal
always accessed without a wait state. The internal peripheral I/O area is also not subject
to programmable wait, and only wait control from each peripheral function is performed.
not access an external memory area other than the one for this initialization routine until
the initial settings of the DWC0 register are complete. However, external memory areas
whose initial settings are complete may be accessed.
DWn2
15
7777H
0
0
0
0
0
0
1
1
1
1
7
DWn1
DW32
DW12
14
0
0
1
1
0
0
1
1
6
R/W
CHAPTER 5 BUS CONTROL FUNCTION
DW31
DW11
DWn0
CS3
User’s Manual U15905EJ2V1UD
CS1
Address:
13
5
0
1
0
1
0
1
0
1
Number of wait states inserted in CSn space (n = 0 to 3)
None
1
2
3
4
5
6
7
DW30
DW10
FFFFF484H
12
4
11
0
0
3
DW22
DW02
10
2
DW21
DW01
CS0
CS2
9
1
DW20
DW00
8
0

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