UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 213

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.2
(2) Prescaler compare register (PRSCM)
(1) Count clock of watch timer
(2) Interval timer
Cautions 1. Do not change the value of the PRSCM register during transmission/reception.
This is an 8-bit compare register.
It can be read or written in 8-bit or 1-bit units.
The clock (f
The relationship between the main clock oscillation frequency (f
BGCSn (m), the set value of the PRCSM register (N), and the output clock (f
Example: Where f
Remark
This timer generates a baud rate interrupt request (INTBRG) at preset time intervals.
The interval time can be set by using the BGCS1 and BGCS0 bits of the prescaler mode register (PRSM) and
the prescaler compare register (PRSCM).
The interval time can be calculated by the following expression.
Generation of clock
2. Set the PRSCM register before setting the CE bit of the PRSM register to 1.
3. Set the PRSM and PRSCM registers in accordance with the main clock frequency to be
PRSCM
used, so that the frequency of f
f
Interval time = f
f
N:
After reset:
BRG
BRG
BRG
: Count clock
) input to the watch timer can be corrected to 32.768 kHz or equivalent frequency.
= f
Value of compare register in prescaler 3 (1 to FFH)
N = 256 if the value of the compare register is “00H”.
X
X
/(2
PRSCM7
= 4.00 MHz, m = 0 (BGCS1 = BGCS = 0), N = 3DH, f
00H
m
× N × 2)
X
/(2
CHAPTER 6 CLOCK GENERATION FUNCTION
PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0
R/W
m
× N)
Address:
User’s Manual U15905EJ2V1UD
BRG
FFFFF8B1H
is 32.768 kHz.
X
), the set value of input clock selection bit
BRG
BRG
= 32.768 kHz
) is as follows:
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