UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 360

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

358
(2) IIC status register (IICS)
Note This register is also cleared when a bit manipulation instruction is executed for bits other than IICS.
Remark
After reset:
IICS
The IICS register is used to indicate the status of I
The IICS register is read-only, in 8-bit or 1-bit units.
This register is cleared to 00H after reset.
LREL: Bit 6 of IIC control register (IICC)
IICE:
Condition for clearing (EXC = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• After reset
Condition for clearing (MSTS = 0)
• When a stop condition is detected
• When ALD = 1
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• After reset
Condition for clearing (ALD = 0)
• Automatically cleared after IICS is read
• When IICE changes from 1 to 0
• After reset
MSTS
MSTS
00H
EXC
ALD
0
1
0
1
0
1
Bit 7 of IIC control register (IICC)
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. MSTS is cleared.
Extension code was not received.
Extension code was received.
R
ALD
Address:
EXC
FFFFFD86H
COI
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
Detection of extension code reception
Note
TRC
Detection of arbitration loss
2
C.
Master device status
2
ACKD
C BUS
Condition for setting (MSTS = 1)
• When a start condition is generated
Condition for setting (ALD = 1)
• When the arbitration result is a “loss”.
Condition for setting (EXC = 1)
• When the higher four bits of the received address
data is either “0000” or “1111” (set at the rising
edge of the eighth clock).
STD
SPD
(1/3)