UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 428

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

426
Reset
Non-
maskable
Software
exception
Exception
trap
Maskable
Type
Notes 1. Execute a system reset after interrupt servicing is finished. It is impossible to restore by executing the
Interrupt
Interrupt
Exception
Exception
Interrupt
2. n = 0 to FH
3.
Classification
RETI instruction.
µ
PD703200Y, 703201Y, 70F3201Y, 703204Y, 70F3204Y only
Default
Priority
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
−
−
−
−
−
−
0
1
2
3
4
5
6
7
8
9
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
RESET
NMI
INTWDT
TRAP0n
TRAP1n
ILGOP/
DBG0
INTWDTM
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTRTC
INTCC00
INTCC01
INTOVF0
INTCC10
INTCC11
INTOVF1
INTTM2
INTTM3
INTTM4
INTTM5
INTCSI0
INTIIC
INTCSI1
INTSRE0
INTSR0
INTST0
INTCSI2
Name
Note 3
Note 2
Note 2
Table 17-1. Interrupt Source List (1/2)
RESET pin input
WDT overflow
NMI pin valid edge input
WDT overflow
TRAP instruction
TRAP instruction
Illegal opcode/
DBTRAP instruction
Interval timer overflow
INTP0 pin valid edge input
INTP1 pin valid edge input
INTP2 pin valid edge input
INTP3 pin valid edge input
INTP4 pin valid edge input
INTP5 pin valid edge input
INTP6 pin valid edge input
RTC interrupt
CC00 capture trigger input/
TM0-CC00 match
CC01 capture trigger input/
TM0-CC01 match
TM0 overflow
CC10 capture trigger input/
TM1-CC10 match
CC11 capture trigger input/
TM1-CC11 match
TM1 overflow
TM2-CR2 match/
TM2 overflow
TM3-CR3 match/
TM3 overflow
TM4-CR4 match/
TM4 overflow
TM5-CR5 match/
TM5 overflow
CSI0 transfer completion
I
CSI1 transfer completion
UART0 reception error
UART0 reception completion UART0
UART0 transmission
completion
CSI2 transfer completion
2
C transfer completion
User’s Manual U15905EJ2V1UD
Trigger
Note 1
(WDTRES) WDT
Pin
Pin
WDT
WDT
Pin
Pin
Pin
Pin
Pin
Pin
Pin
RTC
TM0
TM0
TM0
TM1
TM1
TM1
TM2
TM3
TM4
TM5
CSI0
I
CSI1
UART0
UART0
CSI2
Generating
2
C
Unit
−
−
−
0000H
0010H
0020H
004nH
005nH
0060H
0080H
0090H
00A0H
00B0H
00C0H
00D0H
00E0H
00F0H
0100H
0110H
0120H
0130H
0140H
0150H
0160H
0170H
0180H
0190H
01A0H
01B0H
01C0H
01D0H
01E0H
01F0H
0200H
0210H
Exception
Code
Note 2
Note 2
00000000H
00000010H
00000020H
00000040H
00000050H
00000060H
00000080H
00000090H
000000A0H
000000B0H
000000C0H
000000D0H
000000E0H
000000F0H
00000100H
00000110H
00000120H
00000130H
00000140H
00000150H
00000160H
00000170H
00000180H
00000190H
000001AH
000001B0H
000001C0H
000001D0H
000001E0H
000001F0H
00000200H
00000210H
Address
Handler
Undefined
nextPC
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nextPC
nextPC
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nextPC
nextPC
nextPC
nextPC
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nextPC
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nextPC
nextPC
nextPC
nextPC
Restored
PC
WDTIC
PIC0
PIC1
PIC2
PIC5
PIC6
RTCIC
CCIC00
CCIC01
OVFIC0
CCIC10
CCIC11
OVFIC1
TMIC2
TMIC3
TMIC4
TMIC5
CSIIC0
IICIC0
CSIIC1
SREIC0
SRIC0
STIC0
CSIIC2
PIC3
PIC4
Interrupt
Register
Control
−
−
−
−
−
−