UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 248

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UPD70F3201YGC-YEU-A

Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet

Specifications of UPD70F3201YGC-YEU-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.4
8.4.1
count value preset in 8-bit timer compare register n (CRn).
register is cleared to 0 and counting is continued, and at the same time, an interrupt request signal (INTTMn) is
generated.
246
8-bit timer/event counter n operates as an interval timer that repeatedly generates interrupts at the interval of the
If the count value in 8-bit timer counter n (TMn) matches the value set in the CRn register, the value of the TMn
Remark
Setting method
Basic operation
<1> Set each register.
<2> When the TMCEn bit of the TMCn register is set to 1, the count operation starts.
<3> When the values of the TMn register and CRn register match, INTTMn is generated (TMn register is
<4> Then, INTTMn is repeatedly generated at the same interval. To stop counting, set TMCEn = 0.
Operation
Operation as interval timer (8 bits)
Caution During interval timer operation, do not rewrite the value of the CRn register.
• TCLn register: Selects the count clock (t).
• CRn register:
• TMCn register: Stops count operation and selects the mode in which clear & start occurs on a match
cleared to 00H).
TMn count value
n = 2 to 5
Count clock
INTTMn
TMCEn
CRn
Compare value (N)
between the TMn register and CRn register (TMCn register = 0000xxx0B, ×: don’t
care).
Count start
Figure 8-2. Timing of Interval Timer Operation (1/2)
00H
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TO 5
Interval time = (N + 1) × t: N = 00H to FFH
N
01H
t
User’s Manual U15905EJ2V1UD
N
Clear
Interrupt acknowledgment Interrupt acknowledgment
00H
N
Interval time
01H
N
Clear
00H
N
Interval time
01H
N
N

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