UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 433

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.2.2 Restore
(1) From NMI
(2) From INTWDT
Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during non-
Remark
Execution is restored from the NMI by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
<1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is
<2> Transfers control back to the address of the restored PC and PSW.
The following illustrates how the RETI instruction is processed.
Execution cannot be returned from INTWDT by the RETI instruction. Execute a system reset after the interrupt
has been serviced.
0 and the NP bit of the PSW is 1.
maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by
the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the
LDSR instruction immediately before the RETI instruction.
The solid line shows the CPU processing flow.
1
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Original processing restored
PC
PSW
RETI instruction
Figure 17-3. RETI Instruction Processing
PSW.NP
PSW.EP
0
0
EIPC
EIPSW
User’s Manual U15905EJ2V1UD
1
PC
PSW
FEPC
FEPSW
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