UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 221

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Timer mode control registers 01 and 11 (TMC01 and TMC11)
The TMCn1 registers control the operation of TMn (n = 0, 1).
These registers can be read or written in 8-bit units.
These registers are set to 20H after reset.
Cautions 1. The various bits of the TMCn1 register must not be changed during timer operation. If
(n = 0, 1)
TMCn1
2. If the ENTOn and ALVn bits are changed at the same time, a glitch (spike shaped noise)
3. TOn output is not changed by an external interrupt signal (INTPn0 or INTPn1). To use the
After reset:
they are to be changed, they must be changed after setting the TMCEn bit of the TMCn0
register to 0. If these bits are overwritten during timer operation, operation cannot be
guaranteed (n = 0, 1).
may be generated in the TOn pin output. Either create a circuit configuration that will not
malfunction even if a glitch is generated or make sure that the ENTOn and ALVn bits do
not change at the same time (n = 0, 1).
TOn signal, specify that the capture/compare registers are compare registers (CMSn0 and
CMSn1 bits of TMCn1 register = 1) (n = 0, 1).
• When OSTn bit = 0, output of the ALVn bit inactive level to the TOn pin is fixed.
• When OSTn bit = 1, a compare register match causes TOn output to change.
• If either CCn0 or CCn1 is specified as a capture register, the ENTOn bit must be
When OSTn bit = 1, the TMCEn bit of TMCn0 remains at 1. Counting is restarted by
writing 1 to the TMCEn bit.
ENTOn
OSTn
OSTn
20H
The TOn pin level is not changed even if a match signal from the corresponding
compare register is generated.
However, if capture mode is set, TOn output does not change. The ALVn bit
inactive level is output from the time when timer output is enabled until a match
signal is first generated.
set to 0.
0
1
0
1
7
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
After the overflow, counting continues (free-running mode).
After the overflow, the timer maintains the value 0000H, and counting
stops (overflow stop mode).
External pulse output is disabled.
External pulse output is enabled.
R/W
ENTOn
6
Address:
User’s Manual U15905EJ2V1UD
Setting of operation when TMn register overflowed
ALVn
5
External pulse output (TOn) enable/disable
TMC01 FFFFF608H
ETIn
4
CCLRn
3
ECLRn
TMC11 FFFFF618H
2
CMSn1
1
CMSn0
0
(1/2)
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