UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 424

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.11 Precautions
422
<1> DMA request response time
<2> Memory access
(1) The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA
(2) DMA transfer of 16-bit bus width misaligned data is not supported.
(3) The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer
Notes 1. One clock is always inserted between a read cycle and a write cycle in DMA transfer.
(4) The CPU can access external memory, on-chip peripheral I/O, and internal RAM not undergoing DMA transfer.
(5) Set the VSWC register to 00H or 01H. For details of the VSWC register, refer to CHAPTER 5 BUS CONTROL
(6) Set the DSAn, DDAn, DBCn, and DADCn registers at any of the following timing other than during DMA
(7) If the DSAn or DDAn register is read during DMA transfer, the value being updated may be read.
Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1
objects (external memory, internal RAM, or peripheral I/O) during DMA transfer.
are shown below.
While data transfer among external memories or to and from I/O is being performed, the CPU can access
internal RAM.
While data transfer is being executed between internal RAMs, the CPU can access external memory and
peripheral I/O.
FUNCTION.
operation.
• After reset and before the first DMA transfer starts
• After the channel has been initialized and before the first DMA transfer starts
• After DMA transfer is complete (the TCn bit of the DCHCn register is 1) and before the next DMA transfer
start request is generated
2. If an external interrupt (INTPn) is specified as the trigger to start DMA transfer, noise elimination time is
3. Two clocks are required for a DMA cycle.
4. More wait cycles are necessary for accessing a special internal peripheral I/O register (for details, refer
added (n = 0 to 7).
to 3.4.8 (2)).
destination memory access (<2>)
DMA Cycle
External memory access
Internal RAM access
Peripheral I/O register access
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U15905EJ2V1UD
4 clocks (MIN.) + Noise elimination time
Depends on connected memory.
2 clocks
3 clocks + Number of wait cycles specified by VSWC register
Note 3
Minimum Number of Execution Clocks
Note 2
Note 1
+ Transfer
Note 4