UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 45

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

[V850ES/SA3]
Port CM is a 6-bit I/O port that can be set to the input or output mode in 1-bit units.
Besides functioning as I/O port pins, in the control mode PCM0 to PCM5 also operate as the bus hold control
signal output and bus clock output pins, and as the control signal that inserts a wait state (WAIT) in the bus
cycle.
(a) Port mode
(b) Control mode
PCM0 to PCM5 can be set to the input or output mode in 1-bit units by using port mode register CM
(PMCM).
(i) HLDAK (hold acknowledge) … Output
(ii) HLDRQ (hold request) … Input
(iii) CLKOUT (clock output) … Output
(iv) WAIT (wait) … Input
This pin outputs an acknowledge signal indicating that the V850ES/SA3 has made the address bus,
data bus, and control bus go into a high-impedance state, in response to a bus hold request.
While this signal is active, the address bus, data bus, and control bus are in the high-impedance state.
This pin is used by an external device to request the V850ES/SA3 to release the address bus, data
bus, and control bus. A signal can be input to this pin asynchronously to CLKOUT. When this pin is
active, the V850ES/SA3 makes the address bus, data bus, and control bus go into a high-impedance
state immediately or after completion of the bus cycle under execution, if any, and then asserts the
HLDAK signal and releases the bus.
This pin outputs the internally generated bus clock.
This pin inputs a control signal that inserts a wait state in the bus cycle. The signal is sampled at the
fall of the CLKOUT signal of the T2 and TW states of the bus cycle in the multiplexed mode, and at the
rise of the CLKOUT signal immediately after the T1 and TW states of the bus cycle in the separate
mode.
The wait function is turned on/off by port mode control register CM (PMCCM).
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15905EJ2V1UD
43