UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 277

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UPD70F3201YGC-YEU-A

Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet

Specifications of UPD70F3201YGC-YEU-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
10.4.2 Operation as interval timer
count value set in advance as the interval, by setting bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to
0.
flags (WDTPR0 to WDTPR2) of the WDTIC register are valid and maskable interrupt request signals (INTWDTM) can
be generated. The default priority of the INTWDTM signal is set to the highest level among the maskable interrupt
request signals.
the IDLE mode. Therefore, set the RUN bit of the WDTM register to 1 before the software STOP mode or IDLE mode
is entered in order to clear the interval timer.
The watchdog timer can be made to operate as an interval timer that repeatedly generates interrupts using the
When the watchdog timer operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification
The interval timer continues to operate in the HALT mode, but it stops operating in the software STOP mode and
Cautions 1. Once the WDTM4 bit is set to 1 (thereby selecting the watchdog timer mode), the interval timer
2. When the subclock is selected for the CPU clock, the count operation of the watchdog timer
Remark
2
2
2
2
2
2
2
2
mode is not entered as long as a reset does not occur.
stops (the value of the watchdog timer is maintained).
14
15
16
17
18
19
20
22
/f
/f
/f
/f
/f
/f
/f
/f
XX
XX
XX
XX
XX
XX
XX
XX
Clock
f
XX
: Main clock frequency
819
1.638 ms
3.277 ms
6.554 ms
13.11 ms
26.21 ms
52.43 ms
209.7 ms
f
XX
CHAPTER 10 WATCHDOG TIMER FUNCTIONS
Table 10-3. Interval Time of Interval Timer
µ
= 20 MHz
s
User’s Manual U15905EJ2V1UD
964
1.928 ms
3.855 ms
7.710 ms
15.42 ms
30.84 ms
61.68 ms
246.7 ms
f
XX
µ
= 17 MHz
s
Interval Time
1.214 ms
2.427 ms
4.855 ms
9.709 ms
19.42 ms
33.84 ms
77.67 ms
310.7 ms
f
XX
= 13.5 MHz
2.048 ms
4.096 ms
8.192 ms
16.38 ms
32.77 ms
65.54 ms
131.1 ms
524.3 ms
f
XX
= 8 MHz
275

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