UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 193

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.4
register (AWC). Address wait insertion is set for each chip select area (CS0 to CS3).
address hold wait is inserted, it seems that the low-clock period of T1 state is extended by 1 clock.
Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control
If an address setup wait is inserted, it seems that the high-clock period of T1 state is extended by 1 clock. If an
(1) Address wait control register (AWC)
Caution Be sure to set bits 15 to 8 to 1.
This register can be read or written in 16-bit units.
Programmable address wait function
CSn signal
After reset:
AWC
AHW3
AHWn
ASWn
15
FFFFH
1
7
0
1
0
1
CS3
Not inserted
Inserted
Not inserted
Inserted
ASW3
14
1
6
CHAPTER 5 BUS CONTROL FUNCTION
R/W
Specifies insertion of address setup wait (n = 0 to 3)
Specifies insertion of address hold wait (n = 0 to 3)
AHW2
User’s Manual U15905EJ2V1UD
13
Address:
1
5
CS2
ASW2
FFFFF488H
12
1
4
AHW1
11
1
3
CS1
ASW1
10
1
2
AHW0
9
1
1
CS0
ASW0
1
8
0
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