UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 48

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

46
(12) PDH0 to PDH5 (Port DH) (V850ES/SA2) … 3-state I/O
[V850ES/SA2]
Port DH is a 6-bit port that can be set to the input or output mode in 1-bit units.
Besides functioning as I/O port pins, in the control mode PDH0 to PDH5 also operate as the address bus pins
when the memory is expanded externally.
(a) Port mode
(b) Control mode
[V850ES/SA3]
Port DH is an 8-bit port that can be set to the input or output mode in 1-bit units.
Besides functioning as I/O port pins, in the control mode PDH0 to PDH7 also operate as the address bus pins
when the memory is expanded externally.
(a) Port mode
(b) Control mode
PDH0 to PDH7 (Port DH) (V850ES/SA3) … 3-state I/O
(iii) RD (read strobe) … Output
(iv) ASTB (address strobe) … Output
PDH0 to PDH5 can be set to the input or output mode in 1-bit units by using port mode register DH
(PMDH).
(i) A16 to A21 (address bus 16 to 21) … Output
PDH0 to PDH7 can be set to the input or output mode in 1-bit units by using port mode register DH
(PMDH).
(i) A16 to A23 (address bus 16 to 23) … Output
This is the read strobe signal output pin for the external 16-bit data bus.
This is the latch strobe signal output pin of the external address bus. The output signal goes low at the
falling edge of the T1 state in the bus cycle, and goes high at the falling edge of the T3 state. It is high
when the bus cycle is not active.
These pins form a 6-bit address output bus to access an external device. The output signal changes
at the rising edge of the T1 state in the bus cycle. The address of the immediately preceding bus cycle
is retained when the bus cycle is inactive.
These pins form an 8-bit address output bus to access an external device. The output signal changes
at the rising edge of the T1 state in the bus cycle. The address of the immediately preceding bus cycle
is retained when the bus cycle is inactive.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15905EJ2V1UD