UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 290

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4 Operation
11.4.1 Conversion operation
11.4.2 Conversion operation (power fail monitoring function)
registers.
288
• Setting ADCS of the A/D converter mode register (ADM) to 1 starts conversion of the signal input to the channel
• If ADM, ADS, the power fail comparison threshold register (PFT), or the power fail comparison mode register
• If ADCS is set to 0 during conversion, conversion is interrupted and the conversion operation is stopped.
• For whether or not the conversion end interrupt request signal (INTAD) is generated, refer to 11.4.2.
The conversion end interrupt request signal (INTAD) can be controlled as follows using the PFM and PFT
Note If reading is not performed during this interval, the conversion result changes to the next conversion result.
specified by the analog input channel specification register (ADS). Upon completion of the conversion, the
conversion result is stored in the A/D conversion result register (ADCR) and a new conversion starts.
(PFM) is written during conversion, conversion is interrupted and the conversion operation starts again from the
beginning.
Remark
PFEN Bit
Conversion operation
0
1
1
PFM Register
When PFEN = 1, because the conversion result is overwritten after INTAD has been output
unless the conversion result is read by the time the next conversion ends, in some cases it may
appear as if the actual operation differs from the operation described above (refer to Figure
11-4).
Figure 11-4. Power Fail Monitoring Function (PFCM = 0)
INTAD
ADCR
Don’t care
PFCM Bit
PFT
0
1
Table 11-4. INTAD Signal Control
80H
CHAPTER 11 A/D CONVERTER
INTAD signal is output each time A/D conversion ends
INTAD signal is output only if conversion result (ADCRH) ≥ PFT
INTAD signal is output only if conversion result (ADCRH) < PFT
User’s Manual U15905EJ2V1UD
ANI0
80H
ANI0
Note
Operation
7FH
ANI0
80H
ANI0