UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 422

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.7 Transfer Object
16.7.1 Transfer type and transfer object
disabled).
16.7.2 External bus cycles during DMA transfer (two-cycle transfer)
420
Table 13-2 shows the relationship between transfer type and transfer object (√: Transfer enabled, ×: Transfer
Caution The operation is not guaranteed for combinations of transfer destination and source marked with
Remark
The external bus cycles during DMA transfer (two-cycle transfer) are shown below.
Note Other external cycles such as a CPU-based bus cycle can be started.
On-chip peripheral I/O, internal RAM
External I/O
External memory
“×” in Table 16-2.
During two-cycle 16-bit transfer, if the data bus width of the transfer source and that of the transfer
destination are different, the operation becomes as follows.
In the case of transfer from a 16-bit bus to an 8-bit bus
In the case of transfer from an 8-bit bus to a 16-bit bus
A 16-bit read cycle is generated and then an 8-bit write cycle is generated twice.
An 8-bit read cycle is generated twice and then a 16-bit write cycle is generated.
Transfer Object
On-chip
External I/O
Internal RAM
External memory
Internal ROM
Table 16-3. External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
Table 16-2. Relationship Between Transfer Type and Transfer Object
peripheral I/O
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER)
Internal ROM
None
×
×
×
×
×
Yes
Yes
User’s Manual U15905EJ2V1UD
Note
Peripheral I/O
SRAM cycle
Memory access cycle set by the BCT register
On-Chip
√
√
√
√
×
External I/O
Destination
External Bus Cycle
√
√
√
√
×
Internal RAM
–
√
√
×
√
×
External
Memory
√
√
√
√
×