UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 333

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.7 Cautions
Cautions to be observed when using UARTn are shown below.
(1) When the supply of clocks to UARTn is stopped (for example, in IDLE or STOP mode), operation stops with
(2) When the UARTCAEn bit is set to 0, the UARTn unit is asynchronously reset. The output of the TXDn pin goes
(3) Do not change the values of the following control registers when the TXEn bit or RXEn bit is 1.
(4) To initialize the transmission or reception status, time corresponding to two cycles of the source clock (f
(5) To successively transmit data, confirm the value of the TXBFn bit and then write data to the TXBn register.
(6) Clear the UARTCAEn bit to 0 before rewriting the CKSRn register.
(7) Always read the RXBn register, even when a reception error has occurred.
(8) UARTn has a 2-stage buffer configuration consisting of transmit buffer register n (TXBn) and the transmit shift
each register retaining the value it had immediately before the supply of clocks was stopped. The TXDn pin
output also holds and outputs the value it had immediately before the supply of clocks was stopped. However,
operation is not guaranteed after the supply of clocks is restarted. Therefore, after the supply of clocks is
restarted, the circuits should be initialized by setting UARTCAEn = 0, RXEn = 0, and TXEn = 0 in the ASIMn
register.
to high level.
To operate the UARTn unit, set the UARTCAEn bit to 1, and then set the other bits (TXEn bit = 1, RXEn bit =
1).
To stop the UARTn unit, clear the TXEn and RXEn bits to 0, and then clear the UARTCAEn bit to 0.
• PSn1, PSn0, CLn, SLn, and ISRMn bits of ASIMn register
• BRGCn register
Before changing the values of the above registers, clear the TXEn or RXEn bit to 0.
The operation when the above values are changed with the TXEn or RXEn bit set to 1 is prohibited.
required after clearing the TXEn bit or RXEn bit to 0.
Writing data to the TXBn register is prohibited when the TXBFn bit is 1 (write disabled state).
Unless read, the reception error status (OVEn bit = 1) continues indefinitely.
register, and has status flags (the TXBFn and TXSFn bits of the ASIFn register) that indicate the status of each
buffer. If the TXBFn and TXSFn bits are read in continuous transmission, the value changes from 10 to 01, but
since this change timing is in the period in which data is shifted from TXBn to the transmit shift register, 11 or
00 may be read, depending on the timing. Thus, read only the TXBFn bit during continuous transmission.
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
User’s Manual U15905EJ2V1UD
CKSR
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