UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 442

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3.4 Interrupt control register (xxICn)
conditions for each maskable interrupt request.
440
An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control
This register can be read or written in 8-bit or 1-bit units.
This register is set to 47H after reset.
Caution Read the xxIFn bit of the xxICn register with interrupts disabled (DI). If the xxIFn bit is read with
The addresses and bits of the interrupt control registers are as follows.
Note The flag xxlFn is reset automatically by the hardware if an interrupt request is acknowledged.
Remark
interrupts enabled (EI), a normal value may not be read when the timing of interrupt
acknowledgment and reading of the bit conflict.
xx: Identification name of each peripheral unit (OV, P00 to P03, P10 to P13, CM, DMA, CSI, SE, SR,
n: Peripheral unit number (None or 0 to 3).
xxICn
After reset:
ST, AD)
xxPRn2
xxMKn
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
xxIFn
xxIFn
47H
<7>
0
1
0
1
0
0
0
0
1
1
1
1
Interrupt request not issued
Interrupt request issued
Interrupt servicing enabled
Interrupt servicing disabled (pending)
R/W
xxPRn1
xxMKn
<6>
0
0
1
1
0
0
1
1
Address:
xxPRn0
User’s Manual U15905EJ2V1UD
0
1
0
1
0
1
0
1
0
FFFFF110H to FFFFF15AH
Specifies level 0 (highest).
Specifies level 1.
Specifies level 2.
Specifies level 3.
Specifies level 4.
Specifies level 5.
Specifies level 6.
Specifies level 7 (lowest).
Interrupt request flag
0
Interrupt mask flag
Interrupt priority specification bit
0
xxPRn2
Note
xxPRn1
xxPRn0