UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 367

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5 I
The transfer timing for the “start condition”, “data”, and “stop condition” output via the I
shown below.
The following section describes the I
The master device outputs the start condition, slave address, and stop condition.
The acknowledge signal (ACK) can be output by either the master or slave device (normally, it is output by the
device that receives 8-bit data).
The serial clock (SCL) is continuously output by the master device. However, in the slave device, SCL’s low-level
period can be extended and a wait can be inserted.
(1) Start condition
2
A start condition is met when the SCL pin is at high level and the SDA pin changes from high level to low level.
The start conditions for the SCL pin and SDA pin are signals that the master device outputs to the slave device
when starting a serial transfer. The slave device includes hardware for detecting start conditions.
A start condition is output when bit 1 (STT) of the IIC control register (IICC) is set to 1 after a stop condition
has been detected (SPD: Bit 0 = 1 in IIC status register (IICS)). When a start condition is detected, bit 1 (STD)
of IICS is set to 1.
C Bus Definitions and Control Methods
SDA
SCL
Start
condition
Address
1 to 7
Figure 15-6. I
R/W
8
SDA
SCL
2
C bus’s serial data communication format and the signals used by the I
ACK
9
Figure 15-7. Start Conditions
H
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
2
C Bus Serial Data Transfer Timing
1 to 7
Data
8
2
C BUS
ACK
9
1 to 7
Data
8
ACK
2
C bus’s serial data bus is
9
Stop
condition
2
C bus.
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