UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 197

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.9
external bus cycle.
(successive).
accesses due to bus size limitations.
5.10 Boundary Operation Conditions
5.10.1 Program space
5.10.2 Data space
data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least
twice, causing the bus efficiency to drop.
Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the
Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch
An instruction fetch may be inserted between the read access and write access in a read-modify-write access.
If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between
(1) If a branch instruction exists at the upper limit of the internal RAM area, a prefetch operation straddling over
(2) Instruction execution to the external memory area cannot be continued without a branch from the internal ROM
The V850ES/SA2 and V850ES/SA3 have an address misalign function.
With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword
(1) Halfword-length data access
(2) Word-length data access
Bus Priority
the internal peripheral I/O area (invalid fetch) does not occur.
area to the external memory area.
A byte-length bus cycle is generated twice if the least significant bit of the address is 1.
(a) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if
(b) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10.
the least significant bit of the address is 1.
Priority
High
Low
CHAPTER 5 BUS CONTROL FUNCTION
Bus hold
DMA transfer
Operand data access
Instruction fetch (branch)
Instruction fetch (successive)
User’s Manual U15905EJ2V1UD
Table 5-4. Bus Priority
External Bus Cycle
External device
DMAC
CPU
CPU
CPU
Bus Master
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