UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 250

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.4.2
8-bit timer counter n (TMn).
register is incremented. Either the rising edge or the falling edge can be specified as the valid edge.
register is cleared to 0 and an interrupt request signal (INTTMn) is generated.
248
The external event counter counts the number of clock pulses input to the TIn pin from an external source by using
Each time the valid edge specified by timer clock selection register n (TCLn) is input to the TIn pin, the TMn
When the count value of the TMn register matches the value of 8-bit timer compare register n (CRn), the TMn
Remark
Setting method
<1> Set each register.
<2> When the TMCEn bit of the TMCn register is set to 1, the counter counts the number of pulses input from
<3> When the values of the TMn register and CRn register match, INTTMn is generated (TMn register is
<4> Then, INTTMn is generated each time the values of the TMn register and CRn register match.
Operation as external event counter (8 bits)
TMn count value
Caution During external event counter operation, do not rewrite the value of the CRn register.
Remark
• TCLn register: Selects the TIn input edge.
• CRn register:
• TMCn register: Stops count operation, selects the mode in which clear & start occurs on a match
TIn.
cleared to 00H).
Figure 8-3. Timing of External Event Counter Operation (with Rising Edge Specified)
n = 2 to 5
INTTMn
TMCEn
INTTMn is generated when the valid edge of TIn is input N + 1 times: N = 00 to FFH
CRn
TIn
n = 2 to 5
Count start
00H
Falling edge of TIn pin → TLCn = 00H
Rising edge of TIn pin → TCLn = 01H
Compare value (N)
between the TMn register and CRn register, disables timer output F/F inversion
operation, and disables timer output.
(TMCn register = 0000xx00B, ×: don’t care)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TO 5
01H
02H
User’s Manual U15905EJ2V1UD
03H
04H
05H
N
N Ð 1
N
00H
01H
02H
03H