UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 370

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

368
(4) Acknowledge signal (ACK)
The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data
reception.
The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device
normally receives an ACK signal after transmitting 8 bits of data. However, when the master device is the
receiving device, it does not output an ACK signal after receiving the final data to be transmitted. The
transmitting device detects whether or not an ACK signal is returned after it transmits 8 bits of data. When an
ACK signal is returned, the reception is judged as normal and processing continues. If the slave device does
not return an ACK signal, the master device outputs either a stop condition or a restart condition and then
stops the current transmission. Failure to return an ACK signal may be caused by the following two factors.
When the receiving device sets the SDA line to low level during the ninth clock, the ACK signal becomes active
(normal receive response).
When bit 2 (ACKE) of the IIC control register (IICC) is set to 1, automatic ACK signal generation is enabled.
Transmission of the eighth bit following the 7 address data bits causes bit 3 (TRC) of the IIC status register
(IICS) to be set. When the TRC bit’s value is 0, it indicates receive mode. Therefore, ACKE should be set to
1.
When the slave device is receiving (when TRC = 0), if the slave device does not need to receive any more
data after receiving several bytes, setting ACKE to 0 will prevent the master device from starting transmission
of the subsequent data.
Similarly, when the master device is receiving (when TRC = 0) and the subsequent data is not needed and
when either a restart condition or a stop condition should therefore be output, setting ACKE to 0 will prevent
the ACK signal from being returned. This prevents the MSB data from being output via the SDA line (i.e.,
stops transmission) during transmission from the slave device.
When the local address is received, an ACK signal is automatically output in synchronization with the falling
edge of the eighth clock of SCL regardless of the ACKE bit value. No ACK signal is output if the received
address is not a local address.
The ACK signal output method during data reception is based on the wait timing setting, as described below.
When 8-clock wait is selected: The ACK signal is output at the falling edge of the eighth clock of SCL if ACKE
When 9-clock wait is selected: The ACK signal is automatically output at the falling edge of the eighth clock of
<1> Reception was not correctly performed.
<2> The final data was received.
SDA
SCL
AD6
is set to 1 before wait cancellation.
SCL if ACKE has already been set to 1.
1
AD5
Figure 15-10. ACK Signal
2
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
AD4
3
AD3
4
2
AD2
C BUS
5
AD1
6
AD0
7
R/W ACK
8
9