UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 210

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4
6.4.1
6.4.2
(PCC).
register of port CM is manipulated (refer to 4.3.9 Port CM).
it is √ (operable). When it is × (stops), it outputs a low level. Immediately after reset <1> and in the operation status of
<2>, the alternate function of the CLKOUT pin is used (PCM1: input mode), and therefore the pin goes into a high-
impedance state.
208
The following table shows the operation status of each clock.
Note The watchdog timer clock (f
Remarks CLS bit: Bit 6 of PCC register
The clock output function allows the CLKOUT pin to output the internal system clock (f
The internal system clock (f
The CLKOUT pin functions alternately as the PCM1 pin and operates as a clock output pin when the control
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1, and can output the clock when
Main resonator (f
Sub-resonator (f
CPU clock (f
Internal system clock (f
Peripheral clock (f
WDT clock (f
RTC clock (sub)
RTC clock (main)
Operation
Operation of each clock
Clock output function
processor clock control register (PCC) is set to 1.
MCK bit: Bit 4 of PCC register
√: Operable
×: Stops
<1>: RESET pin input
<2>: During oscillation stabilization time count
<3>: HALT mode
<4>: IDLE mode
<5>: Software STOP mode
<6>: Subclock operation mode
<7>: Sub-IDLE mode
CPU
XW
)
)
XT
X
)
XX
)
to f
CLK
XX
/512)
)
CLK
) is selected by using the CK3 to CK0 bits of the processor clock control register
CHAPTER 6 CLOCK GENERATION FUNCTION
Table 6-1. Operation Status of Each Clock
XW
<1>
) is operable but it stops operating in the watchdog timer if the CLS bit of the
×
√
×
×
×
×
√
×
User’s Manual U15905EJ2V1UD
<2>
√
√
×
×
×
√
√
√
MCK Bit = 0
CLS Bit = 0
<3>
√
√
×
√
√
√
√
√
<4>
√
√
×
×
×
×
√
√
<5>
×
√
×
×
×
×
√
×
Note
<6>
MCK Bit = 0
CLS Bit = 1
√
√
√
√
√
√
√
CLK
<7>
).
√
√
×
×
×
×
√
√
<6>
MCK Bit = 1
CLS Bit = 1
×
√
√
√
×
×
√
×
<7>
×
√
×
×
×
×
√
×