UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 310

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
(4) Receive buffer register n (RXBn)
The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the receive
shift register.
When reception is enabled (RXEn bit = 1 in the ASIMn register), receive data is transferred from the receive
shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame.
Also, a reception completion interrupt request (INTSRn) is generated by the transfer to the RXBn register. For
information about the timing for generating this interrupt request, refer to 13.5 (4) Receive operation.
If reception is disabled (RXEn bit = 0 in the ASIMn register), the contents of the RXBn register are retained,
and no processing is performed for transferring data to the RXBn register even when the shift-in processing of
one frame is completed. Also, no reception completion interrupt is generated.
When 7 bits is specified for the data length, bits 6 to 0 of the RXBn register are transferred for the receive data
and the MSB (bit 7) is always 0. However, if an overrun error (OVEn) occurs, the receive data at that time is
not transferred to the RXBn register.
Except when a reset is input, the RXBn register becomes FFH even when UARTCAEn = 0 in the ASIMn
register.
This register is read-only, in 8-bit units.
This register is set to FFH after reset.
After reset:
FFH
R
Address: RXB0
FFFFFA02H, RXB1 FFFFFA12H
7
6
5
4
3
2
1
0
RXBn
RXBn7
RXBn6
RXBn5
RXBn4
RXBn3
RXBn2
RXBn1
RXBn0
(n = 0, 1)
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User’s Manual U15905EJ2V1UD