UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 322

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

320
INTSRn (output)
(Reception completion
INTSREn (output)
(Reception error
interrupt)
INTSRn (output)
(Reception completion
INTSREn (output)
(Reception error
interrupt)
interrupt)
interrupt)
(a) Separation of reception error interrupt
(a) No error occurs during reception
(a) No error occurs during reception
A reception error interrupt can be separated from the INTSRn interrupt and generated as the INTSREn
interrupt by clearing the ISRMn bit of the ASIMn register to 0.
Figure 13-9. When Reception Error Interrupt Is Separated from
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
Figure 13-10. When Reception Error Interrupt Is Included in
Reception Completion Interrupt (INTSRn) (ISRMn Bit = 1)
Reception Completion Interrupt (INTSRn) (ISRMn Bit = 0)
User’s Manual U15905EJ2V1UD
INTSRn (output)
(Reception completion
INTSREn (output)
(Reception error
interrupt)
INTSRn (output)
(Reception completion
interrupt)
INTSREn (output)
(Reception error
interrupt)
interrupt)
(b) An error occurs during reception
(b) An error occurs during reception
INTSRn
does not occur
INTSREn
does not occur