UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 363

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) IIC clock selection register (IICCL)
Note Bits 4 and 5 are read-only bits.
Remark
IICCL
After reset:
The IICCL register is used to set the transfer clock for I
The IICCL register can be read or written in 8-bit or 1-bit units. Set the SMC, CL1, and CL0 bits in combination
with the CLX bit of the IIC function expansion register (IICX) (see Table 15-2 Transfer Clock Setting).
This register is cleared to 00H after reset.
IICE: Bit 7 of IIC control register (IICC)
Condition for clearing (CLD = 0)
• When the SCL line is at low level
• When IICE = 0
• After reset
Condition for clearing (DAD = 0)
• When the SDA line is at low level
• When IICE = 0
• After reset
The digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary regardless of DFC switching (on/off).
DAD
SMC
00H
CLD
DFC
0
1
0
1
0
1
0
1
0
SCL line was detected at low level.
SCL line was detected at high level.
SDA line was detected at low level.
SDA line was detected at high level.
Operates in standard mode.
Operates in high-speed mode.
Digital filter off.
Digital filter on.
R/W
0
Note
CLD
Address:
Detection of SDA line level (valid only when IICE = 1)
Detection of SCL line level (valid only when IICE = 1)
FFFFFD84H
DAD
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
Digital filter operation control
SMC
Operation mode switching
2
C.
2
C BUS
Condition for setting (CLD = 1)
• When the SCL0 line is at high level
Condition for setting (DAD = 1)
• When the SDA line is at high level
DFC
CL1
CL0
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