UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 237

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
(4) Cycle measurement
By setting the TMCn0 and TMCn1 registers as shown in Figure 7-15, the 16-bit timer/event counter can
measure the cycle of signals input to the INTPn0 or INTPn1 pin.
The valid edge of the INTPn0 pin is selected according to the IESn01 and IESn00 bits of the SESn register,
and the valid edge of the INTPn1 pin is selected according to the IESn11 and IESn10 bits of the SESn register.
Either the rising edge, the falling edge, or both edges can be selected as the valid edges of both pins.
If the CCn0 register is set as a capture register, the valid edge input of the INTPn0 pin is set as the trigger for
capturing the TMn register value in the CCn0 register. When this value is captured, an INTCCn0 interrupt is
generated.
Similarly, if the CCn1 register is set as a capture register, the valid edge input of the INTPn1 pin is set as the
trigger for capturing the TMn register value in the CCn1 register. When this value is captured, an INTCCn1
interrupt is generated.
The cycle of signals input to the INTPn0 pin is calculated by obtaining the difference between the TMn
register’s count value (Dx) that was captured in the CCn0 register according to the x-th valid edge input of the
INTPn0 pin and the TMn register’s count value (D(x+1)) that was captured in the CCn0 register according to
the (x+1)-th valid edge input of the INTPn0 pin and multiplying the value of this difference by the cycle of the
internal count clock.
The cycle of signals input to the INTPn1 pin is calculated by obtaining the difference between the TMn
register’s count value (Dx) that was captured in the CCn1 register according to the x-th valid edge input of the
INTPn1 pin and the TMn register’s count value (D(x+1)) that was captured in the CCn1 register according to
the (x+1)-th valid edge input of the INTPn1 pin and multiplying the value of this difference by the cycle of the
internal count clock.
Remark
n = 0, 1
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User’s Manual U15905EJ2V1UD