UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 466

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.4 Software STOP Mode
18.4.1 Setting and operation status
register is set to 1 in the normal operation mode.
supply to the CPU and the on-chip peripheral functions is stopped.
was set are retained. The on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator
or an external clock continue operating.
to a level lower than the IDLE mode.
consumption can be minimized with only leakage current flowing.
18.4.2 Releasing software STOP mode
interrupt request (INTP0 to INTP6 pin input), unmasked internal interrupt request from the peripheral functions
operable in the software STOP mode, or RESET pin input.
stabilization time has been secured.
464
Non-maskable interrupt request
Maskable interrupt request
The software STOP mode is set when the PSM bit of the PSMR register is set to 1 and the STP bit of the PSC
In the software STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock
As a result, program execution is stopped, and the contents of the internal RAM before the software STOP mode
Table 18-7 shows the operation status in the software STOP mode.
Because the software STOP mode stops operation of the main clock oscillator, it reduces the power consumption
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
The software STOP mode is released by a non-maskable interrupt request (NMI pin input), unmasked external
After the software STOP mode has been released, the normal operation mode is restored after the oscillation
(1) Releasing software STOP mode by non-maskable interrupt request or unmasked maskable interrupt
request
The software STOP mode is released by a non-maskable interrupt request or an unmasked maskable interrupt
request, regardless of the priority of the interrupt request. If the software STOP mode is set in an interrupt
servicing routine, however, an interrupt request that is issued later is serviced as follows.
(a) If an interrupt request with a priority lower than that of the interrupt request currently being serviced is
(b) If an interrupt request with a priority higher than that of the interrupt request currently being serviced is
issued, only the software STOP mode is released, and that interrupt request is not acknowledged. The
interrupt request itself is retained.
issued (including a non-maskable interrupt request), the software STOP mode is released and that
interrupt request is acknowledged.
Release Source
set the software STOP mode.
Table 18-6. Operation After Releasing Software STOP Mode by Interrupt Request
Execution branches to the handler address
Execution branches to the handler
address or the next instruction is
executed
CHAPTER 18 STANDBY FUNCTION
If the subclock oscillator and external clock are not used, the power
Interrupt Enabled (EI) Status
User’s Manual U15905EJ2V1UD
The next instruction is executed
Interrupt Disabled (DI) Status