YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 1060

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 25 List of Registers
Register Name
Timer general register B_0
Timer general register C_0
Timer general register D_0
Timer control register_1
Timer mode register_1
Timer I/O control register_1
Timer interrupt enable register_1
Timer status register_1
Timer counter_1
Timer general register A_1
Timer general register B_1
Timer control register_2
Timer mode register_2
Timer I/O control register_2
Timer interrupt enable register_2
Timer status rgister_2
Timer counter_2
Timer general register A_2
Timer general register B_2
Notes: 1. If the pulse output group 2 and pulse output group 3 output triggers are the same
Rev.7.00 Mar. 18, 2009 page 992 of 1136
REJ09B0109-0700
2. For writing, refer to section 14.6.1, Notes on Register Access.
3. Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
4. Supported only by the H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm
5. These addresses should not be accessed in the H8S/2375, H8S/2375R, H8S/2373,
according to the PCR setting, the NDRH address will be H'FF4C, and if different, the
address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different,
the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
F-ZTAT Group.
H8S/2373R, H8S/2376, H8S/2377, and H8S/2377R.
Abbrevia-
tion
TGRC_0
TGRD_0
TCNT_1
TCR_2
TMDR_2
TIOR_2
TSR_2
TGRB_0
TCR_1
TMDR_1
TIOR_1
TIER_1
TSR_1
TGRA_1
TGRB_1
TIER_2
TCNT_2
TGRA_2
TGRB_2
Number
of Bits
16
16
16
8
8
8
8
8
16
16
16
8
8
8
8
8
16
16
16
Address Module
H'FFDA
H'FFDC
H'FFDE
H'FFE0
H'FFE1
H'FFE2
H'FFE4
H'FFE5
H'FFE6
H'FFE8
H'FFEA
H'FFF0
H'FFF1
H'FFF2
H'FFF4
H'FFF5
H'FFF6
H'FFF8
H'FFFA
TPU_0
TPU_0
TPU_0
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_1
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
Data
Width
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
2
Access
States
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2