YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 968

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 21 Flash Memory (0.18-μm F-ZTAT Version)
6. The FPEFEQ and FUBRA parameters are set for initialization.
Note: * 8 to 35 MHz in H8S/2378.
7. Initialization
Rev.7.00 Mar. 18, 2009 page 900 of 1136
REJ09B0109-0700
⎯ If the value of the DPFR parameter is different from before downloading, check the SS bit
⎯ The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
⎯ Set the user branch destination address as the FUBRA parameter (general register ER1)
When a programming program is downloaded, the initialization program is also downloaded to
the on-chip RAM. There is an entry point of the initialization program in the area from the start
address specified by FTDAR + 32 bytes of the on-chip RAM. The subroutine is called and
initialization is executed by using the following steps.
MOV.L
JSR
NOP
⎯ The general registers other than ER0, ER1 are held in the initialization program.
⎯ R0L is a return value of the FPFR parameter.
⎯ Since the stack area is used in the initialization program, a stack area of a maximum 128
(bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program
selection and FKEY setting were normal, respectively.
ER0).
The allowable setting range for the FPEFEQ parameter is 8 MHz to 34 MHz * . When the
frequency is set to out of this range, an error is returned to the FPFR parameter of the
initialization program and initialization is not performed. For details on the frequency
setting, see the description in 21.3.2 (2) (a), Flash programming/erasing frequency
parameter (FPEFEQ: general register ER0 of CPU).
and the user branch enable bits (FUBE15 to FUBE0) as the FPEFEQ parameter (general
register ER0). Set FUBRA and FUBE15 to FUBE0 to 0 if the user branch function is not
required.
Do use programmable user MAT as the user branch destination. Also, do not use an area
containing a downloaded internal program as the user branch destination. After user branch
processing completes, use the RTS instruction to return to programming processing.
For details, see the descriptions in 21.3.2 (2) (a), Flash programming/erasing frequency
parameter (FPEFEQ: general register ER0 of CPU), and 21.3.2 (2) (b), Flash user branch
address setting parameter (FUBRA: general register ER1 of CPU).
bytes must be allocated in RAM.
DLTOP+32,ER2;
@ER2;
Set entry address to ER2
Call initialization routine