YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 370

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 7 DMA Controller (DMAC)
Bit
4
3
Rev.7.00 Mar. 18, 2009 page 302 of 1136
REJ09B0109-0700
Bit Name
DTE0
DTIE1B
Initial Value
0
0
R/W
R/W
R/W
Description
Data Transfer Enable 0
Enables or disables DMA transfer for the activation
source selected by the DTF3 to DTF0 bits in
DMACR of channel 0.
When DTE0 = 0, data transfer is disabled and the
activation source is ignored. If the activation source
is an internal interrupt, an interrupt request is
issued to the CPU or DTC. If the DTE0 bit is
cleared to 0 when DTIE0 = 1, the DMAC regards
this as indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU.
When DTE0 = 1 and DTME0 = 1, data transfer is
enabled and the DMAC waits for a request by the
activation source. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
•
•
[Setting condition]
When 1 is written to the DTE0 bit after reading
DTE0 = 0
Data Transfer Interrupt Enable 1B
Enables or disables an interrupt to the CPU or DTC
when transfer on channel 1 is interrupted. If the
DTME1 bit is cleared to 0 when DTIE1B = 1, the
DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either by
clearing the DTIE1B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME1 bit to 1.
When initialization is performed
When the specified number of transfers have
been completed
When 0 is written to the DTE0 bit to forcibly
suspend the transfer, or for a similar reason