YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 791

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.4
Figure 15.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In
asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication. In asynchronous serial communication, the
communication line is usually held in the mark state (high level). The SCI monitors the
communication line, and when it goes to the space state (low level), recognizes a start bit and
starts serial communication. Inside the SCI, the transmitter and receiver are independent units,
enabling full-duplex communication. Both the transmitter and the receiver also have a double-
buffered structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer.
15.4.1
Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 15.5, Multiprocessor Communication Function.
Serial
data
1
Operation in Asynchronous Mode
Data Transfer Format
Start
bit
1 bit
0
LSB
Figure 15.2 Data Format in Asynchronous Communication
D0
One unit of transfer data (character or frame)
(Example with 8-Bit Data, Parity, Two Stop Bits)
D1
D2
Transmit/receive data
D3
7 or 8 bits
D4
Section 15 Serial Communication Interface (SCI, IrDA)
D5
D6
Rev.7.00 Mar. 18, 2009 page 723 of 1136
MSB
D7
Parity
bit
1 bit,
or none
0/1
Stop bit(s)
1
1 or
2 bits
1
REJ09B0109-0700
Idle state
(mark state)
1