YLCDRSK2378 Renesas Electronics America, YLCDRSK2378 Datasheet - Page 340

• Manufacturer Part Number: YLCDRSK2378
• Description: KIT DEV EVAL H8S/2378 LCD
• Manufacturer: Renesas Electronics America
• Series: H8®r

Specifications of YLCDRSK2378

• Main Purpose: Displays, LCD Controller
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: YLCDRSK2378
• Primary Attributes: 5.7" QVGA, Touch Screen
• Secondary Attributes: Source Code on CD, Debugging Requires Emulator Cable E10A USB/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 6 Bus Controller (BSC)
6.11.3
Figure 6.84 shows the timing for transition to the bus released state.
Figure 6.85 shows the timing for transition to the bus released state with the synchronous DRAM
interface.
Rev.7.00 Mar. 18, 2009 page 272 of 1136
REJ09B0109-0700
Address bus
HWR, LWR
Data bus
BREQO
BREQ
BACK
RD
AS
[1] Low level of BREQ signal is sampled at rise of φ.
[2] Bus control signal returns to be high at end of external space access cycle.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.
φ
Transition Timing
At least one state from sampling of BREQ signal.
bus release while BREQOE bit is set to 1, BREQO signal goes low.
External space
access cycle
T
Figure 6.84 Bus Released State Transition Timing
1
[1]
T
2
[2]
[3]
[4]
[5]
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
[6]
[7]
[8]
CPU
cycle